1. Field of the Invention
The present invention generally relates to methods and systems for checking spacing of wiring in a semiconductor structure and more particularly to a method and system for checking the spacing of wiring within a single net.
2. Description of the Related Art
Conventional design rules require wires of the same net within a semiconductor structure to be spaced a specified minimum distance apart. A net can be defined as a set of logically connected shapes (typically terminals on logic gates) which are electrically connected when modeled physically. Older designs satisfied the minimum spacing requirements fairly easily through simplified grid designs which automatically guaranteed that minimum spacing design rules were met. However, with advancing technologies wider wires are more prevalent. Such wide wires have larger spacing requirements than the older narrower wires. Therefore, a simple gridded solution is no longer effective with today's current wide wires.
Minimum spacing violations were conventionally recognized during the shapes processing performed by Design Rules Check (DRC). Design Rules Check is an expensive and time consuming process which is usually run after the final physical design layout is complete. Further, correcting minimum spacing violations after the final physical design layout is complete is also a difficult and expensive process. Therefore, there is a conventional need for a system and method for checking a given net for spacing violations which is fast, inexpensive and can be performed before the final physical design layout is complete.